technical data IN74HC4015A dual 4-bit shift register high-performance silicon-gate cmos ordering information IN74HC4015An plastic IN74HC4015Ad soic t a = -55 to 125 c for all packages the device inputs are compatible with standard cmos outputs; with pullup resistors, they are comp atible with ls/alsttl outputs. this device consists of two identical independent 4-stage serial- input/parallel-output registers. each register has independent clock and reset inputs as well as a single serial data input. ?q? outputs are available from each of the four stages on both registers. a ll register stages are d-type, master-slave flip-flops. the logic level present at the data input is transferred into the first register stage and shifted over one stage at each positive-going clock transition. resetting of all stages is accomplished by a high level on the reset line. ? outputs directly interf ace to cmos, nmos, and ttl ? operating voltage range: 2.0 to 6.0 v ? low input current: 1.0 a ? high noise immunity characteristic of cmos devices pin assignment logic diagram rev. 00 function table inputs outputs clock data reset q 0 q n l l l q n-1 h l h q n-1 x l q 0 * q n * pin 16 = v cc pin 8 = gnd x x h l l * = no change x = don?t care
IN74HC4015A rev. 00 maximum ratings * symbol parameter value unit v cc dc supply voltage (referenced to gnd) -0.5 to +7.0 v v in dc input voltage (referenced to gnd) -1.5 to v cc +1.5 v v out dc output voltage (referenced to gnd) -0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output current, per pin 25 ma i cc dc supply current, v cc and gnd pins 50 ma p d power dissipation in still air, plastic dip+ soic package+ 750 500 mw tstg storage temperature -65 to +150 c t l lead temperature, 1 mm from case for 10 seconds (plastic dip or soic package) 260 c * maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the reco mmended operating conditions. +derating - plastic dip: - 10 mw/ c from 65 to 125 c soic package: : - 7 mw/ c from 65 to 125 c recommended operating conditions symbol parameter min max unit v cc dc supply voltage (referenced to gnd) 2.0 6.0 v v in , v out dc input voltage, output voltage (referenced to gnd) 0 v cc v t a operating temperature, all package types -55 +125 c t r , t f input rise and fall time (figure 1) v cc =2.0 v v cc =4.5 v v cc =6.0 v 0 0 0 1000 500 400 ns this device contains protection circuitry to guard agains t damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage highe r than maximum rated voltages to this high-impedance circuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
IN74HC4015A rev. 00 dc electrical characteristics (voltages referenced to gnd) v cc guaranteed limit symbol parameter test conditions v 25 c to -55 c 85 c 125 c unit v ih minimum high- level input voltage v out = 0.1 v or v cc -0.1 v ?i out ? 20 a 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 v v il maximum low - level input voltage v out =0.1 v or v cc -0.1 v ?i out ? 20 a 2.0 4.5 6.0 0.3 0.9 1.2 0.3 0.9 1.2 0.3 0.9 1.2 v v oh minimum high- level output voltage v in =v ih or v il ?i out ? 20 a 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 v v in = v ih or v il ?i out ? 4.0 ma ?i out ? 5.2 ma 4.5 6.0 3.98 5.48 3.84 5.34 3.7 5.2 v ol maximum low- level output voltage v in =v ih or v il ?i out ? 20 a 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 v v in = v ih or v il ?i out ? 4.0 ma ?i out ? 5.2 ma 4.5 6.0 0.26 0.26 0.33 0.33 0.4 0.4 i in maximum input leakage current v in =v cc or gnd 6.0 0.1 1.0 1.0 a i cc maximum quiescent supply current (per package) v in =v cc or gnd i out =0 a 6.0 8.0 80 160 a
IN74HC4015A rev. 00 ac electrical characteristics (c l =50pf,input t r =t f =6.0 ns) v cc guaranteed limit symbol parameter v 25 c to -55 c 85 c 125 c unit f max maximum clock frequency (50% duty cycle) (figure 2) 2.0 4.5 6.0 6 30 35 4.8 24 28 4 20 24 mhz t plh , t phl maximum propagation delay, clock to q (figures 2 and 5) 2.0 4.5 6.0 175 35 30 220 44 37 265 53 45 ns t phl maximum propagation delay, reset to q (figures 1 and 5) 2.0 4.5 6.0 205 41 35 255 51 43 310 62 53 ns t tlh , t thl maximum output transition time, any output (figures 3 and 5) 2.0 4.5 6.0 75 15 13 95 19 16 110 22 19 ns c in maximum input capacitance - 10 10 10 pf power dissipation capacitance (per latch) typical @25 c,v cc =5.0 v c pd used to determine the no-load dynamic power consumption: p d =c pd v cc 2 f+i cc v cc 140 pf timing requirements (c l =50pf,input t r =t f =6.0 ns) v cc guaranteed limit symbol parameter v 25 c to -55 c 85 c 125 c unit t su minimum setup time, d to clock (figure 4) 2.0 4.5 6.0 50 10 9.0 65 13 11 75 15 13 ns t h minimum hold time, clock to d (figure 4) 2.0 4.5 6.0 5 5 5 5 5 5 5 5 5 ns t rec minimum recovery time, reset to clock (figure 1) 2.0 4.5 6.0 5 5 5 5 5 5 5 5 5 ns t w minimum pulse width, reset (figure 1) 2.0 4.5 6.0 80 16 14 100 20 17 120 24 20 ns t w minimum pulse width, clock (figure 4) 2.0 4.5 6.0 80 16 14 100 20 17 120 24 20 ns t r , t f maximum input rise and fall times (figure 1) 2.0 4.5 6.0 1000 500 400 1000 500 400 1000 500 400 ns
IN74HC4015A figure 1. switching waveforms figure 2. switching waveforms figure 3. switching waveforms figure 4. switching waveforms figure 5. test circuit rev. 00
IN74HC4015A expanded logic diagram rev. 00
IN74HC4015A n suffix plastic dip (ms - 001bb) symbol min max a 18.67 19.69 b 6.1 7.11 c 5.33 d 0.36 0.56 f 1.14 1.78 g h j 0 10 k 2.92 3.81 notes: l 7.62 8.26 1. dimensions ?a?, ?b? do not include mold flash or protrusions. m 0.2 0.36 maximum mold flas h or protrus ions 0.25 mm (0.010) per s ide. n 0.38 d suffix soic (ms - 012ac) symbol min max a 9.8 10 b 3.8 4 c 1.35 1.75 d 0.33 0.51 f 0.4 1.27 g h j 0 8 notes: k 0.1 0.25 1. dimensions a and b do not include mold flash or protrusion. m 0.19 0.25 2. maximum mold flas h or protrus ion 0.15 mm (0.006) per s ide p 5.8 6.2 for a; for b ? 0.25 mm (0.010) per s ide. r 0.25 0.5 5.72 2.54 7.62 1.27 dimens ion, mm dimens ion, mm a b h c k c m j f m p g d r x 45 seating plane 0.25 (0.010) m t -t- 1 16 8 9 l h m j a b f g d seating plane n k 0.25 (0.010) m t -t- c 1 16 8 9 rev. 00
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